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Huawei Unveils 'LogicFolding' Architecture and 'Tau Scaling Law' — Here's What's Actually New

Huawei Unveils 'LogicFolding' Architecture and 'Tau Scaling Law' — Here's What's Actually New
Huawei didn't just announce a timeline — it revealed the specific engineering method it plans to use to get there. 'LogicFolding' stacks 2D circuits into 3D vertical structures, bypassing the EUV machines China can't legally touch. The company also says it already quietly built 381 chips using this approach over the last six years.

The Part Most Headlines Buried

Everyone reported the 2031 target date. Almost nobody explained how Huawei actually plans to get there.

At the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai on May 25, 2026, He Tingbo — Huawei's board member and president of its HiSilicon semiconductor division — didn't just drop a roadmap. He unveiled a complete architectural framework the company has been secretly developing for six years.

What 'LogicFolding' Actually Means

Traditional chipmakers shrink transistors — physically making them smaller. That requires Extreme Ultraviolet (EUV) lithography machines made by the Dutch firm ASML. China can't buy those. U.S. sanctions, expanded repeatedly since 2019, specifically blocked that access.

Huawei's answer: stop trying to shrink, and start stacking.

The "LogicFolding" architecture, according to Tom's Hardware, folds traditional flat 2D circuit designs into 3D vertical structures — essentially building upward instead of inward. Think skyscrapers instead of sprawl, as NBC News described it.

The result, Huawei claims, is a 55% increase in transistor density compared to its current process — without needing EUV equipment at all.

The 'Tau Scaling Law' — Moore's Law Is Dead, Says Huawei

Huawei also introduced something called the Tau Scaling Law — which some in the industry are already calling "He's Law" after He Tingbo, according to SemiWiki.

Moore's Law, the decades-old principle that transistor counts double roughly every two years, works by shrinking physical size. The Tau Scaling Law flips that entirely. It focuses on reducing the time — or latency — it takes for signals to move through a chip, scaling through system-level efficiency rather than geometry.

This is a genuine architectural philosophy change designed specifically around China's constraints. If you can't shrink the transistor, make the signal move faster.

381 Chips Already Built — This Isn't Vaporware

A critical detail separates this announcement from typical press conference announcements.

According to Tom's Hardware, Huawei didn't just announce the LogicFolding concept — He Tingbo revealed the company has already designed and mass-produced 381 chips based on the Tau Scaling Law methodology during those six years of secret development.

The first public product using LogicFolding architecture is Huawei's flagship Kirin smartphone processors, debuting this autumn.

SemiWiki reported that the upcoming Kirin chip is targeting 238 million transistors per square millimeter (MTr/mm²) — a density that rivals TSMC's 3nm process. China's current best, from Semiconductor Manufacturing International Corp (SMIC), is 7nm — what appears in Huawei's existing Mate 60 phones.

Moving from 7nm-equivalent to 3nm-equivalent in one generation, without EUV, using a fundamentally different architecture, represents a significant engineering claim.

What Mainstream Coverage Got Wrong

Most outlets framed this purely as a geopolitical "defiance" story. China vs. America. Huawei vs. sanctions. That framing isn't wrong — but it skips the engineering.

NBC News at least explained the 3D stacking concept clearly. Engadget focused almost entirely on the 2031 date and the cost angle — He Tingbo described the process as "feasible and affordable," citing The Wall Street Journal — without digging into LogicFolding mechanics.

Mainstream coverage has not adequately addressed the 381 already-built chips. This is the single most important data point in the entire announcement, suggesting this is not a PowerPoint presentation but a program with an established track record.

The Honest Caveat

NBC News noted it plainly: Huawei provided zero independent performance data to support its claims at the symposium.

Claiming 238 MTr/mm² and actually delivering it in volume production are two different things. TSMC's 1.4nm process — which it says will enter mass production in 2028 — will still have a three-year head start on Huawei's 2031 target, even if Huawei hits its numbers exactly.

And "transistor density equivalent" carries significant weight in this announcement. Huawei is achieving comparable density through 3D stacking and architectural tricks — not the same underlying process node. Whether real-world performance matches is a question only independent benchmarks can answer. Those don't exist yet.

What This Means for Regular People

If Huawei's Kirin chips this autumn deliver anywhere near 3nm-equivalent performance, it validates the entire Tau/LogicFolding framework — and signals that U.S. sanctions are not stopping China's semiconductor advancement, only redirecting it.

China building competitive AI chips domestically shifts the strategic calculation that Washington has been operating on. The implications extend across sectors dependent on semiconductor access and AI capability.

The 2031 date is five years away. The autumn Kirin launch is months away. Independent performance benchmarks will be the decisive measure.

Sources

center-left Engadget Huawei claims it will make cutting-edge semiconductors by 2031
center-left nbcnews China’s Huawei touts chip design breakthrough in bid to defy U.S. sanctions
unknown tomshardware Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law | Tom's Hardware
unknown semiwiki Huawei plans 1.4-nm chips by 2031, Kirin 2026 Chip: 238 MTr/mm2 transistor density rivaling TSMC’s 3nm | SemiWiki